Uyemura, John P. <br/><br/>
Chip design for submicron VLSI  CMOS layout and simulation  Textual Documents 

 - New Delhi  Ceanage Learning India   2006 
<br/><br/><label>Subjects--Index Terms: </label>Gate array technology 
<br/><br/><label>Dewey Class. No.: </label>621.395